F3 Inc.Products

FMYF2 is a highly integrated CO/CPE MC (Media Converter). The FMYF2 is designed specifically for frame-based OAM that satisfies 5 ways of loop-back tests.

The FMYF2 integrates one 10/100Base-TX and one 100Base-FX transceivers. Both have embedded packet memory, a switch controller and OAM (Operation, Administration, and Maintenance) control logic into a single CMOS integrated circuit. It may connect to an O/E module or a transformer.

The FMYF2 provides 10/100 auto-negotiation capability for 10/100Base-TX ports. Only 10/100Base-TX port could support Full-Duplex and Half-Duplex modes. In half-duplex mode, the controller supports back-pressure congestion control to avoid packet loss during a long burst of traffic. In full-duplex mode of operation, The FMYF2 supports symmetric IEEE802.3x flow control. With hardware switching engine, The FMYF2 can switch at Full-Duplex wire rate. Totally 1K MAC addresses filtering and aging function are supported.

· IEEE802.3 compliant. Auto-negotiation or flow control, duplex modes and speeds.

· Wire speed Store-and-Forward switching with low switching latency.

· Supports up to 1K unicast MAC addresses and unlimited number of broadcast addresses. Uses

2-layer hashing table with 1 hashing algorithms, aging time is set to 300sec

· 16K Bytes Packet Buffer per Port.

· Supports 2047 Bytes of maximum frame size.

· Switching at wire rate.

· Supports Half & Full Duplex Operation.

· Optional Back-Pressure Flow Control for half-duplex operation.

· Optional IEEE 802.3x Flow Control for full-duplex operation.

· Support multiple interfaces in order for any specific application to do additional functions

· Support Far End Fault enable function consistent with IEEE802.3 standard.

· Support to transceive data (10Mb/s) on standard CAT5 UTP cable over 300 meters. (F3 patent)

· Single 50 MHz operation, 3.3V/2.5V dual power, low power 0.25u CMOS technology.

· 128pins PQFP package.

Datasheet download V1.0

Application Note V1.0

Application V1.0