¡P IEEE802.3 (2000 Edition)
compliant
¡P Five/Three
10BASE-T transceivers included in one single chip.
¡P On-chip FIFO, PLL, Manchester
encoder/decoder
¡P Automatic polarity detection and
correction
¡P Automatic partitioning of faulty ports
¡P Rich-function LED drivers support for
per port link/ receive, partition, collision status and
high priority port utilization.
¡P Embedded pre-distortion resistor for
every TP port
¡P Support to transceiver data with which
F3¡¦s declared on standard CAT5 UTP cable over
300 meters. ( F3 patent
pending )
¡P MII/SNI interface easily interface with
CPU
¡P Data steering/mirroring for security,
authentication, authorization, and so on
¡P F3 proprietary high priority frame
control. ( F3 patent pending )
¡P Low Power CMOS technology with a single
+5V supply
¡P 44-pin QFP for FH3VS, 100-pin QFP for FH5VS
¡@
Datasheet download V1.0
Application V2.0
¡@