The FYG/FYG-46 is a 1.25Gb/s Ethernet Transceiver (SerDes) optimized for Gigabit Ethernet or 1000Base-X  applications. It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK and serializes it onto the TX PECL differential outputs at a baud rate that is ten times the REFCLK frequency. The FYG/FYG-46 also samples serial received data on the RX PECL differential inputs, recovers the clock and data, de-serializes it onto the 10-bit received data bus, outputs two recovered clocks at one-twentieth of the incoming baud rate and detects “Comma” characters. The FYG/FYG-46 contains on-chip PLL circuitry for synthesis of the transmit clock, and extraction of the clock from the received serial stream. These circuits are fully monolithic and require no external components.